1. Field of the Invention
The present invention relates to an arithmetic unit for performing arithmetic operations such as a multiplication operation, a multiply-add operation and a multiply-subtract operation on fixed-point numbers.
2. Description of the Background Art
It has become common to provide, as an on-chip component, an arithmetic unit such as a multiplier unit, a multiply-add unit, etc., in an LSI for digitally processing sound data, multimedia data, and the like. For processes for which high-precision operations are required, an arithmetic unit of this type performs operations with fixed-point numbers represented as two's complements. In such operations on fixed-point numbers, it is required to perform a saturation operation when a multiplication result overflows. Specifically, an n-bit fixed-point number can take values in the range of −2n to +2n−1 (or 100 . . . 00 to 011 . . . 11 in binary representation), and a multiplication result will overflow (i.e., exceed the range of positive values that can be properly represented) if the multiplicand and the multiplier are both the smallest value (a negative value with the largest absolute value). Therefore, a saturation operation is performed so as to correct the multiplication result to the largest positive representable value.
As shown in FIG. 17, for example, a conventional unit capable of such a saturation operation includes a partial product generator 901 for producing a plurality of partial products of a multiplicand A and a multiplier B, an adder 902 for adding together the produced partial products, an overflow detection unit 903 for detecting the presence/absence of an overflow, and a selector 904 for selectively outputting either the addition result from the adder 902 or the saturated value (largest positive value) according to the presence/absence of an overflow. Therefore, if an overflow occurs (i.e., if the multiplicand A and the multiplier B are both the negative value with the largest absolute value), the saturated value is selected, thus correcting the multiplication result.
However, in a case where the selection between the output from the adder 902 and the saturated value is made by the selector 904, a multiplication result that does not overflow is obtained only after the delay through the selector 904 since when it is output from the adder 902.
In view of this, there have been proposed arithmetic units employing the Booth's algorithm, in which if an overflow occurs, a Booth encoder outputs a predetermined value on which a multiplication operation is performed to give the saturated value (see, for example, Japanese Laid-Open Patent Publication No. 1-267728).
However, such a method can only be applicable to arithmetic units including a Booth encoder. Moreover, even with such a Booth encoder, it is not always easy to actually improve the operation speed. That is, where the Booth encoder is controlled based on the presence/absence of an overflow, the amount of time required for the overflow detection operation adds to the total operation time. Therefore, even though there is no delay due to a selector, the total operation time is increased by the amount of time required for the overflow detection operation, whereby the operation speed may not always be improved.